IBM Unveils Sub-1 Nanometer Chip With 100 Billion Transistors, Extending Moore’s Law

A New Architecture, Not Just a Smaller Chip

The announcement centers connected what IBM calls the “nanostack,” an wholly caller three-dimensional transistor architecture developed astatine its semiconductor probe installation successful Albany, New York. The plan stacks and staggers transistors vertically successful 2 bonded layers, utilizing an ultra-thin dielectric worldly to abstracted them.

That attack differs fundamentally from the nanosheet exertion IBM pioneered and the broader manufacture adopted. Nanosheets compressed features successful 2 dimensions. Nanostack adds density successful a third.

“We’re not conscionable making smaller transistors, we’re reinventing however chips are built to present dramatically much powerfulness and vigor efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow.

What the Numbers Show

IBM’s published method results, presented astatine VLSI 2026, study the pursuing compared to IBM’s 2 nm spot from 2021:

• Nearly 2x transistor density
• Up to 50% much performance
• Up to 70% greater vigor efficiency
• 40% betterment successful SRAM scaling

The SRAM summation matters specifically for AI workloads. On-chip representation bandwidth is simply a limiting origin for AI accelerators, and amended SRAM scaling lets spot designers acceptable much representation person to the processor without adding country oregon powerfulness draw.

Why the 0.7 nm Label Needs Context

Modern process node numbers nary longer correspond to literal carnal dimensions. The transistor transmission layers successful IBM’s nanostack plan measurement astir 5 nanometers thick, oregon astir 15 silicon atoms. The 0.7 nm designation reflects the density and show generation, not a nonstop measurement of each diagnostic connected the chip.

IBM acknowledged this directly. The company’s presumption is that the nanostack method delivers the effectual gains expected from sub-1 nm scaling by going vertical alternatively than by shrinking each magnitude person to atomic limits.

A Path Forward for Moore’s Law

The semiconductor manufacture has faced mounting unit arsenic accepted two-dimensional shrinking hits carnal constraints, including quantum tunneling, vigor dissipation, and manufacturing cost. The gait of gains from axenic lithography improvements has slowed.

IBM’s attack addresses this by adding density done 3D sequential integration. The institution projects the nanostack architecture tin enactment astatine slightest a decennary of continued scaling from this point.

Dan Hutcheson of Techinsights said the improvement puts “another 10, 15 years connected the roadmap.”

Major competitors similar Intel, Samsung, and TSMC are pursuing related three-dimensional transistor strategies, including complementary FET designs. IBM’s announcement represents a moving objection of a verified way astatine the sub-1 nm threshold.

The Albany Research Ecosystem

IBM conducts this enactment alongside partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions. The Albany installation volition besides location a High Numerical Aperture Extreme Ultraviolet lithography instrumentality from ASML, a strategy required for the adjacent signifier of logic scaling.

IBM separately announced plans to signifier Anderon, a standalone quantum foundry intended to manufacture quantum wafers astatine commercialized scale.

Timeline to Production

The nanostack spot remains a probe prototype, though IBM confirmed it has demonstrated functional CMOS inverter cognition with expected switching performance. IBM sees a way to accumulation adoption successful arsenic aboriginal arsenic 5 years, oregon astir 2031.

The announcement does not awesome an imminent merchandise release. It signals that the industry’s adjacent procreation of hardware has a viable structural foundation.